1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a nonvolatile memory device capable of performing an erase operation in units of pages, and a nonvolatile memory system including the nonvolatile memory device.
2. Description of the Related Art
In general, a NAND type flash memory device includes a plurality of cell blocks. One cell block (also called a “sector”) includes a plurality of cell strings in which a plurality of cells are serially connected to one another, a plurality of bit lines, a plurality of word lines, drain selection transistors connected between the cell strings and the bit lines, and source selection transistors connected between the cell strings and common source lines.
Meanwhile, a plurality of memory cells sharing one word line constitute one or more pages, and all cells share a P well. Furthermore, the NAND type flash memory device further includes pass transistors for supplying a given voltage to the cell block, where the pass transistors include a drain selection transistor of a high voltage transistor, a source selection transistor of a high voltage transistor, and a cell selection transistor of a high voltage transistor.
The NAND type flash memory device configured as above performs an erase operation prior to a program operation, in which data is programmed in a selected cell. The program operation of the NAND type flash memory device is performed in units of pages, but the erase operation is performed in units of cell blocks because all the cells share the P well. An erase operation of the conventional NAND type flash memory device will be briefly described below.
One of the cell blocks is selected, and then a power supply voltage is supplied to gates of the drain selection transistor, the source selection transistor, and the cell selection transistor within the pass transistor coupled to the selected cell block. Next, a voltage of 4.5 V is supplied to the drain selection transistor and the source selection transistor, and a voltage of 0 V is supplied to a memory cell through the cell selection transistor. On the other hand, a voltage of 0 V is supplied to the gate of the drain selection transistor, the source selection transistor, and the cell selection transistor coupled to an unselected cell block. Then, an erase voltage is supplied to P wells of all the cell blocks. However, when the P well of the unselected cell is increased by the erase voltage, a word fine voltage of the unselected cell is increased by a coupling effect due to capacitance of a word line and capacitance between the word line and the P well, and thus, the unselected cell block may not be erased.
The conventional NAND type flash memory device, in which the erase operation is performed in units of cell blocks as described above, has a limitation in updating data. In other words, to correct a part of the data, it may be necessary to perform a process of writing data for all cells within one cell block to correct a part of the data. That is, in the case in which 64 or 128 pages typically constitute one cell block, it is necessary to perform erase operations to the 64 or 128 pages and additional moving operations corresponding data to another cell block in order to correct a part of the data.
Therefore, if an erasable unit is subdivided into a unit other than a block unit, it may be possible to ensure the use expandability of the NAND type flash memory device.